UART-Based Integrated Logic Analyzer

This module provides the ILA as a streaming UART device, for use with the UART backhaul interface. It does this by wrapping the StreamILA and providing the output stream of the ILA capture data as a UART port using the Torii AsyncSerialTX

The baud rate for the UART stream is adjustable, but the UART stream itself is fixed to 8n1.

class torii_ila.uart.UARTIntegratedLogicAnalyzer(*, divisor: int, tx: Signal, signals: Iterable[Signal] = [], sample_depth: int = 32, sampling_domain: str = 'sync', sample_rate: float = 60000000.0, prologue_samples: int = 1) → None

A simple ILA that dumps sample memory down a UART pipe.

The configuration is 8n1 at the baud dictated by the divisor, which should be int(clk // baud) for the desired baud rate.

Parameters:

  • divisor (int) – The clock divisor needed on the output domain to reach the desired baudrate.

  • tx (Signal) – The UART Transmit signal to use.

  • signals (Iterable[torii.Signal]) – The signals to capture with the ILA. (default: list()) (default: [])

  • sample_depth (int) – Number of samples we wish to capture. (default: 32) (default: 32)

  • sampling_domain (str) – The clock domain the ILA sampling will take place on. (default: sync) (default: 'sync')

  • sample_rate (float) – The outwards facing sample rate used for formatting output. This should be tied to the sampling_domain’s frequency if possible. (default: 60e6 i.e 60MHz) (default: 60000000.0)

  • prologue_samples (int) – The number of samples to capture before the trigger. (default: 1) (default: 1)

Attributes:

  • domain (str) – The domain the ILA is sampling on.

  • ila (IntegratedLogicAnalyzer) – The inner ILA module used for actually ingesting the sample data.

  • sample_width (int) – The width of the sample vector in bits.

  • sample_depth (int) – The depth of the ILA sample buffer in samples.

  • sample_rate (float) – The outwards facing sample rate used for formatting output

  • sample_period (float) – The period of time between samples in nanoseconds, equivalent to 1 / sample_rate.

  • bits_per_sample (int) – The nearest power of 2 number of bits per sample.

  • bytes_per_sample (int) – The number of whole bytes per sample.

  • trigger (Signal, in) – ILA Sample start trigger strobe.

  • sampling (Signal, out) – Indicates when the ILA is actively sampling.

  • complete (Signal, out) – Indicates when sampling is completed and the buffer is full.

  • idle (Signal, out) – Indicates the UART transmitter is sitting idle and is ready to send data.

get_backhaul(port: Serial) → UARTIntegratedLogicAnalyzerBackhaul

Automatically create a UARTIntegratedLogicAnalyzerBackhaul from this ILA instance.

Parameters:

port (serial.Serial) – The serial port to use to ingest data from.

Returns:

The newly constructed backhaul interface or the already constructed instance.

Return type:

UARTIntegratedLogicAnalyzerBackhaul

add_signal(sig: Signal) → None

Add a signal to the ILA capture list.

This can be used to internal module signals to the ILA, or add signals after construction.

Note

This method must not be called post elaboration, as we are unable to adjust the sample memory size after is it made concrete.

Parameters:

sig (torii.Signal) – The signal to add to the ILA capture list.

Raises:

RuntimeError – If called during the elaboration of the ILA module

Return type:

None

append_signals(signals: Iterable[Signal]) → None

Like add_signal() but allows for adding an array of signals to the ILA capture list.

Note

This method must not be called post elaboration, as we are unable to adjust the sample memory size after is it made concrete.

Parameters:

signals (Iterable[torii.Signal]) – The list of additional signals to capture with the ILA.

Raises:

RuntimeError – If called during the elaboration of the ILA module

Return type:

None